NOVOSENSE NSi6801C DSWFR single channel isolated gate driver with 80 nanoseconds propagation delay
Product Overview
The NSi6801 is a single-channel isolated gate driver, pin-compatible with popular opto-coupled gate drivers. It is designed to drive IGBTs, power MOSFETs, and SiC MOSFETs in applications such as motor control systems, solar inverters, and power supplies. The device offers 5A peak source and sink current, with 5700Vrms isolation per UL1577 in a Strenched-SO6 package. It boasts a minimum common-mode transient immunity (CMTI) of 100kV/us and operates with a maximum supply voltage of 35V and a 13V UVLO. Compared to standard opto-isolated gate drivers, the NSi6801 provides improved reliability, aging performance, higher operating temperature, shorter propagation delay, and reduced pulse width distortion, making it an ideal replacement in high reliability, power density, and efficiency switching power systems.
Key Features
- Isolated single-channel driver
- Pin compatible, drop in upgrade for opto isolated gate drivers
- Driver side supply voltage: up to 35V with 13V UVLO
- 5A peak source and 5A peak sink output current
- High CMTI: 100kV/us
- 80ns typical propagation delay
- 35ns maximum pulse width distortion
- 25ns maximum part to part delay matching
- Accepts minimum input pulse width 30ns
- Operation ambient temperature: -40C ~125C
- RoHS-compliant packages: SOIC-6 wide body DUB-8
Safety Regulatory Approvals
- UL recognition: 5700Vrms for 1 minute per UL1577
- DIN VDE V 0884-11:2017-01
- CSA component notice 5A
- CQC certification per GB4943.1-2011
Applications
- Isolated DC/DC and AC/DC power supplies in server, telecom and industry
- High Voltage PFC
- DC-to-AC solar inverters
- Motor drives and EV charging
- UPS and battery chargers
Technical Specifications
| Parameter | Symbol | Min | Typ | Max | Unit | Condition |
| Absolute Maximum Ratings | ||||||
| Average Input Current | IF_AVG | 25 | mA | |||
| Peak Transient Input Current | IF_PEAK | 0.2 | A | |||
| Reverse Input Voltage | VR_MAX | 6.5 | V | |||
| Driver Side Supply Voltage | VCC-VEE | -0.3 | 35 | V | ||
| Output Signal Voltage | VOUT | VEE-0.3 | VCC+0.3 | V | ||
| Operating Junction Temperature | TJ | -40 | 150 | C | ||
| Storage Temperature | Tstg | -65 | 150 | C | ||
| Electrostatic Discharge (HBM) | VESD_HBM | 2000 | V | per AEC-Q100-002-RevD | ||
| Electrostatic Discharge (CDM) | VESD_CDM | 500 | V | per AEC-Q100-011-RevB | ||
| Recommended Operating Conditions | ||||||
| Input Current (ON) | IF(ON) | 7 | 16 | mA | ||
| Input Voltage (OFF) | VF(off) | -5.5 | 0.9 | V | ||
| Driver Side Supply Voltage | VCC- VEE | 14 | 33 | V | ||
| Ambient Temperature | TA | -40 | 125 | C | ||
| DC Electrical Characteristics | ||||||
| Driver Side Supply High Level Supply Current | ICCH | 2 | 3 | mA | IF=10mA, IOUT=0mA | |
| Driver Side Supply Low Level Supply Current | ICCL | 2 | 3 | mA | VF=0V, IOUT=0mA | |
| VCC UVLO Rising Threshold | VCC_ON | 12.5 | 13 | 13.5 | V | IF=10mA |
| VCC UVLO Falling Threshold | VCC_OFF | 11.5 | 12 | 12.5 | V | |
| VCC UVLO Hysteresis | VCC_HYS | 1 | V | |||
| Input Pin Characteristic Input Forward Threshold Current Low to High | IFLH | 1.5 | 2.8 | 4 | mA | VOUT>5V, Cg=1nF |
| Threshold Input Voltage High to Low | VFHL | 0.9 | V | VOUT<5V, Cg=1nF | ||
| Input Forward Voltage | VF | 1.9 | 2.2 | 2.5 | V | IF=10mA |
| Temp Coefficient of Input Forward Voltage | VF/T | 1 | 1.35 | mV/C | IF=10mA | |
| Input Reverse Breakdown Voltage | VR | 6.5 | V | IR=10uA | ||
| Input Capacitance | CIN | 15 | pF | f=0.5MHz | ||
| Output Pin Characteristic High Level Output Voltage | VOH | VCC- | VCC- 0.26 | V | IOUT=-100mA, IF=10mA | |
| Output Pin Characteristic High Level Output Voltage | VOH | VCC- 0.36 | V | IOUT=0mA, IF=10mA | ||
| Low Level Output Voltage | VOL | 40 | 60 | mV | IOUT=100mA, VF=0V | |
| High Level Peak Output Current | IOH | 3 | 5 | A | VCC=15V, pulse width<10us | |
| Low Level Peak Output Current | IOL | 3 | 5 | A | VCC=15V, pulse width<10us | |
| Switching Electrical Characteristics | ||||||
| Minimum Pulse Width | tPWmin | 30 | 40 | ns | CLOAD=1nF, f=20kHz (50% Duty Cycle) | |
| Propagation Delay | tpHL, tpLH | 80 | 105 | ns | ||
| Pulse Width Distortion | |tPLH-tPHL| tPWD | 35 | ns | |||
| Part to Part Delay Matching | tDM | 25 | ns | (1) | ||
| Output Rise Time (20% to 80%) | tR | 28 | ns | |||
| Output Fall Time (80% to 20%) | tF | 25 | ns | |||
| VCC Power-Up Time Delay | tstart_VCC | 20 | us | VCC rising | ||
2410121806_NOVOSENSE-NSi6801C-DSWFR_C5123577.pdf
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