power gate driver Hynetek HP3600 AB001 SP16R with dual channel and under voltage lockout protection
Product Overview
The Hynetek HP3600 is an isolated dual-channel gate driver designed for high-efficiency power applications. It offers robust performance with high common-mode transient immunity (CMTI) and fast propagation delays, making it suitable for driving MOSFET, SiC, and GaN FETs. The device features programmable dead time, fast disable functionality for power sequencing, and comprehensive under-voltage lockout (UVLO) protection on both primary and secondary supplies. Its design ensures reliable operation in demanding environments.
Product Attributes
- Brand: Hynetek Semiconductor Co., Ltd.
- Product Name: HP3600
- Package: SOP-16
- Certifications: VDE (DIN VDE 0884-17:2021-10), UL (UL 1577 component recognition program), CQC (GB4943.1-2022), TUV
- Operating Junction Temperature Range: 40 C to 150 C
Technical Specifications
| Parameter | Symbol | Conditions | Min | Typ | Max | Unit |
| POWER SUPPLY | ||||||
| Input supply voltage | VDDI | 3 | 18 | V | ||
| Input supply quiescent current | IDDI | VINA = 0 V, VINB = 0 V | 1.5 | 2.5 | mA | |
| Input supply operating current | IDDI | Fsw = 50 kHz, current per channel, COUT = 100 pF | 1.9 | 3.1 | mA | |
| Output supply voltage | VDDA/VDDB | 3.5 | 30 | V | ||
| Output supply quiescent current | IVDDA/IVVDB | VINA = 0 V, VINB = 0 V | 0.8 | 2 | mA | |
| Output supply operating current | IVDDA/IVVDB | Fsw = 50 kHz, current per channel, COUT = 100 pF | 1.2 | 2.3 | mA | |
| VDDA/VDDB UNDER VOLTAGE LOCKOUT (UVLO) | ||||||
| UVLO turn-on threshold | VUVLO_ON | 3.2 | 3.5 | 3.8 | V | |
| UVLO turn-off threshold | VUVLO_OFF | 2.7 | 3.0 | 3.3 | V | |
| UVLO threshold hysteresis | VUVLO_HYST | 0.5 | V | |||
| VDDI UNDER VOLTAGE LOCKOUT (UVLO) | ||||||
| UVLO turn-on threshold | VDDI_ON | 2.5 | 2.7 | 2.9 | V | |
| UVLO turn-off threshold | VDDI_OFF | 2.3 | 2.5 | 2.7 | V | |
| UVLO threshold hysteresis | VDDI_HYST | 0.2 | V | |||
| INPUT (INA, INB) | ||||||
| Input voltage threshold for transition Low to High | VINH | 1.7 | 2.1 | V | ||
| Input voltage threshold for transition High to Low | VINL | 0.8 | 1.1 | V | ||
| Input voltage threshold hysteresis | VIN_HYST | 0.4 | 0.8 | 1.2 | V | |
| Pull down Resistance on VIA,VIB,DIS and PWM | RPD | 100 | 170 | 280 | k | |
| DEAD-TIME | ||||||
| Dead time | tDT | RDTC = 20 k | 160 | 200 | 240 | ns |
| OUTPUTS (OUTA, OUTB) | ||||||
| Peak sourcing output current | ISRC_PK | CVDD = 10 F, CLOAD = 0.18 F, Fsw = 1 kHz, bench measurement | 4.0 | A | ||
| Peak sinking output current | ISNK_PK | CVDD = 10 F, CLOAD = 0.18 F, Fsw = 1 kHz, bench measurement | -6.0 | A | ||
| Output voltage at high state | VOHA_ERR/ VOHB_ERR | VVDDA, VVDDB = 12 V, IOUT = 10 mA, TA = 25C | 13 | 24 | mV | |
| Output voltage at low state | VOLA/VOLB | VVDDA, VVDDB = 12 V, IOUT = 10 mA, TA = 25C | 7 | 14 | mV | |
| Switching Characteristics | ||||||
| Output rise time, 10% to 90% measured points | tRISE | COUT = 1.0 nF, Fsw= 1 kHz, 50% duty cycle | 6 | 15 | ns | |
| Output fall time, 90% to 10% measured points | tFALL | 4 | 10 | ns | ||
| Minimum pulse width | tPWmin | Output off for less than minimum, COUT = 0 pF | 15 | ns | ||
| INx/DIS to OUTx turn-on / off propagation delay | tPD_ON / tPD_OFF | 48 | 68 | ns | ||
| Pulse width distortion | tPWD | |tPD_ON - tPD_OFF| | 20 | ns | ||
| Propagation delays matching between VOUTA, VOUTB | tDM | Fsw = 100 kHz | 18 | ns | ||
| VDDI UVLO Recovery Delay | tUVLO_REC_V DDI | 15 | 100 | s | ||
| VDDA, VDDB UVLO Recovery Delay | tUVLO_REC_V DDA/B | 20 | 30 | s | ||
| High Level Static Common Mode Transient Immunity | CMTIH | VCM=1000V, TA=25C | 150 | 200 | kV/s | |
| Low Level Static Common Mode Transient Immunity | CMTIL | VCM=1000V, TA=25C | 150 | 200 | kV/s | |
2410121803_Hynetek-HP3600-AB001-SP16R_C22394788.pdf
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