High Speed Digital Isolators Broadcom HCPL-090J-500E Ideal for Multiplexed Data Transmission Systems
High Speed Digital Isolators
Product Overview
The Broadcom HCPL-90xx and HCPL-09xx series are high-speed CMOS digital isolators featuring excellent transient immunity and industry-leading performance. With a typical pulse width distortion of 2 ns and a propagation delay skew of 4 ns, these devices achieve a 100 Mbaud data rate, making them the fastest digital isolators available. They offer various channel configurations, including single, dual (unidirectional and bidirectional), and quad channels, with high channel density ideal for isolating data conversion devices, parallel buses, and peripheral interfaces. Available in multiple package types (8-pin PDIP, 8-pin Gull Wing, 8-pin SOIC, and 16-pin SOIC narrow/wide body) and specified for operation between 40C and +100C, these isolators are suitable for applications such as digital fieldbus isolation, multiplexed data transmission, computer peripheral interfaces, and isolated data interfaces.
Product Attributes
- Brand: Broadcom
- Certifications: UL1577, IEC 61010-1
- ESD Sensitivity: Handle with normal static precautions
- Not for: Military or aerospace applications
Technical Specifications
| Feature/Model | Specification | Details |
|---|---|---|
| General Features | Compatibility | +3.3V and +5V TTL/CMOS compatible |
| Max. Pulse Width Distortion | 3 ns | |
| Max. Propagation Delay Skew | 6 ns | |
| Max. Propagation Delay | 15 ns | |
| High Speed Data Rate | 100 MBd | |
| Common Mode Rejection | 15 kV/s min. | |
| Isolation Rating | 2500V RMS | |
| Applications | Fieldbus | Digital fieldbus isolation |
| Data Transmission | Multiplexed data transmission | |
| Interfaces | Computer peripheral interface, Isolated data interfaces | |
| Systems | High speed digital systems | |
| Logic | Logic level shifting | |
| Operation | Full-duplex mode for digital fieldbus applications | |
| Models & Configurations | Single Channel | HCPL-9000/-0900 (Active-low logic output enable) |
| Dual Channel Unidirectional | HCPL-9030/-0930 | |
| Dual Channel Bidirectional | HCPL-9031/-0931 | |
| Quad Channel Unidirectional | HCPL-900J/-090J | |
| Quad Channel 2/2 Bidirectional | HCPL-901J/-091J | |
| Quad Channel 1/3 Bidirectional | HCPL-902J/-092J | |
| Package Types | 8-pin PDIP, 8-pin Gull Wing, 8-pin SOIC, 16-pin SOIC (Narrow and Wide Body) | |
| Electrical Specifications (Typical @ +25C) | Supply Voltage | 3.0V to 5.5V |
| Operating Temperature | -40C to +100C | |
| Max. Data Rate | 100 MBd (up to 110 MBd) | |
| Common Mode Transient Immunity | 15 kV/s min. | |
| Package Characteristics | Capacitance (Input-Output) | Single Channel: 1.1 pF, Dual Channel: 2.0 pF, Quad Channel: 4.0 pF |
| Thermal Resistance (JCT) | 8-Pin PDIP: 54 C/W, 8-Pin SOIC: 144 C/W, 16-Pin SOIC Narrow: 41 C/W, 16-Pin SOIC Wide: 28 C/W | |
| Package Power Dissipation (PPD) | 150 mW (all package types) | |
| Creepage Distance (External) | 8-Pin PDIP: 7.04 mm, 8-Pin SOIC: 4.04 mm, 16-Pin SOIC Narrow: 4.03 mm, 16-Pin SOIC Wide: 8.08 mm |
Ordering Information Example
HCPL-9031-500E: 300 mil DIP Gull Wing Surface Mount package, Tape and Reel, RoHS compliant.
Application Information
Power Consumption: Low power consumption achieved by detecting edge transitions and converting them to narrow current pulses. Power consumption is frequency-dependent and independent of mark-to-space ratio. Approximate supply current per channel: I(Input) = 40(f/fmax)(1/4) mA, where fmax = 50 MHz.
Signal Status on Start-up and Shut Down: Input signals are differentiated and latched. Designers should consider an initialization signal for unambiguous output states during power-up, shutdown, or power loss.
Bypassing and PC Board Layout: No external interface circuitry required. Use low ESR 47 nF ceramic capacitors for power supply decoupling, placed close to VDD pins. Ground planes for GND1 and GND2 are recommended for data rates above 10 Mb/s.
Timing Diagrams and Definitions
Propagation Delay: Time for a logic signal to propagate through the isolator (tPLH, tPHL).
Pulse Width Distortion (PWD): Difference between tPHL and tPLH, affecting maximum data rate capability. Typically, 20%-30% of minimum pulse width is tolerable.
Propagation Delay Skew (tPSK) & Channel-to-Channel Skew (tCSK): Critical for parallel data transmission synchronization. tPSK is the difference between min/max propagation delays across devices; tCSK is within a single device. Absolute minimum pulse width in parallel applications is typically twice tPSK.
2411271927_Broadcom-HCPL-090J-500E_C2962876.pdf
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